In connection with the handling and use of integrated circuits (IC), it is necessary to protect the circuit elements and circuit assemblies included therein from the effects of over-voltage conditions. In this regard, over-voltages or over-voltage conditions refer to electrical signals in a voltage range above the normal operating voltage range of the circuit, and in a voltage range that could otherwise damage the circuit. Such over-voltage conditions, for example, typically arise through a discharge of an accumulated static charge, e.g. from people or machine components through the IC or from the IC through people or machine components. Such discharge processes are also commonly referred to as electrostatic discharge or ESD processes.
If such over-voltage signals, which may have an amplitude of several kilovolts, are applied to an integrated circuit, irreversible changes and damage of the components or assemblies of the IC can thereby be caused, for example through thin film burn-out, filamentation and short-circuiting of layer junctions or junction spiking, charge carrier injection into oxide layers, or oxide rupture, which can even lead to total destruction of the entire IC under certain conditions. This danger exists especially in the case of applications in motor vehicles or automobiles in which ICs are typically designed and embodied for processing signals with positive polarity. In this case, if the substrate or ground potential is briefly and temporarily shifted, due to an ESD event, to a potential that is not the lowest potential of the circuit, this can bias diode pathways of circuit components in a forward conducting direction, for example, which in turn can lead to the above mentioned damages of the affected components or entire component assemblies. On the other hand, particularly in applications in the automobile industry, it is desired to enable certain contacts of an IC to be temporarily loaded with a voltage below the ground potential, without this voltage in this regard being limited to the value of a diode forward conducting voltage.
While the above problems arise in conventional bulk technologies (i.e. with a bulk semiconductor substrate), which are mentioned as an example, they are not limited to such a field. Namely, such problems also arise in applications using SOI (Silicon On Insulator) technologies, within the scope of the present invention, and especially in the field of applications in the automobile industry.
In view of the above described danger to integrated circuits represented by ESD effects, it has been known to provide special semiconductor structures for limiting over-voltages in the ICs. Such special semiconductor structures are intended to conduct-away the briefly arising extremely high currents (with a current value of several amperes) associated with ESD events, without causing any damage or disruption of the IC. Moreover, such special semiconductor structures are intended to remain inactive during the normal operation of the IC. In this regard, the special protective structures satisfy their intended functions ever better, the more uniformly they trigger and the lower their ohmic resistance in the triggered state (low power dissipation). In bulk technologies, a buried layer is typically provided in the substrate for reducing the ohmic resistance, but such a buried layer normally does not exist, i.e. is normally not used, in SOI technologies due to reasons of cost and/or difficult practical realization thereof. Moreover, due to the higher wafer prices in connection with SOI applications, it is economically not sensible to simply enlarge the components for achieving a simple adaptation of the resistance.
U.S. Patent Application Publication U.S. 2002/0153564 A1 (Shirai) discloses a previously known conventional semiconductor structure in the above mentioned general field. The known semiconductor structure comprises a lateral bipolar pnp-transistor structure arranged in an n-doped Si layer of an SOI substrate, having p-doped first and second layers that are formed in the Si layer and are spaced apart from one another, an n-doped third layer formed in contact with the second layer in the SI layer, a first electrode (anode) in contact with the first layer, a second electrode (cathode) in contact with the second and third layers, as well as an n-doped fourth layer formed in contact with the second and third layers in the Si layer. Such a structure corresponds to a bipolar pnp-transistor, of which the base and emitter are short-circuited to each other. Furthermore, according to the above mentioned publication, the second, third and fourth layers (cathode side) may, if applicable, be arranged so as to surround the first layer (anode side) essentially in a ring-shape at a certain spacing distance.
Upon the occurrence of a voltage drop between the cathode and the anode, corresponding to a positive ESD pulse applied to the cathode or a negative ESD pulse applied to the anode, this will give rise to a voltage breakdown, whereby a zone that is depleted as to positive charge carriers will expand and extend from the anode side to the cathode side, in connection with a resulting current flow oriented from the cathode to the anode in the conventional sense. The n-doped fourth layer on the cathode side serves to adapt and particularly increase the breakdown voltage.
In the subject matter of the above mentioned publication U.S. 2002/0153564 A1, it is especially disadvantageous, that only a relatively nonuniform breakdown characteristic or behavior can be achieved as a result of local field concentrations or increases due to the concrete embodiment of the disclosed semiconductor structure in the area of the first (anode) layer. The disclosed structure and the resulting relatively non-uniform breakdown behavior are necessarily associated with a corresponding local increased current flow and power or energy transfer. Thus, there still exists a danger of damage to the semiconductor structure especially arising in this local area with an increased or concentrated current flow. In any event, the field of application is constrained with respect to the voltage that is to be limited.
Other conventional semiconductor structures suffering the same or similar disadvantages are disclosed in U.S. Pat. No. 4,862,310 (Harrington, Ill.), U.S. Pat. No. 5,241,210 (Nakagawa et al.), U.S. Pat. No. 6,242,763 (Chen et al.) and in U.S. Patent Application Publication U.S. 2003/0162375 Al (Chen). The semiconductor structures, and the overall subject matters of these publications are, however, in principle not predominantly intended or suitable for use as ESD protective elements.